Reduction of Routing Area in High-Level Synthesis

We address the problem of the wiring area as a result of high-level synthesis. When generating the layout of a circuit by ‘compiling’ a high-level hardware description, generally the netlist is computed after the scheduling and allocation phases. The result of high-level synthesis systems in most cases are interconnection nets based on multiplexer structures with a high connectivity. This results in layouts where the silicon area occupied by the interconnection at RT level has about the same size as the area occupied by the operational components. Although a high connectivity need not to be bad in all cases, we present a possible approach for reducing the wiring area. We replace the multiplexers by bus-oriented structures to avoid the central multiplexer modules which may be as large as the other functional units. The connection logic will become decentralized by using tri-state outputs at all functional units, memories, and registers. However, we also want to start a discussion for high-level synthesis to consider the interconnection already in the earlier synthesis phases. The goal should be the synthesis of circuits where the connectivity is comparable to manual designs without reducing the system performance. But this is not possible by only optimizing the number of functional units first and then computing the netlist from a fixed interconnection graph. Reduction of Routing Area in High-Level Synthesis